1. Field of the Invention
The present invention relates to methods for making semiconductor dice. More specifically, the invention relates to methods and apparatus for balancing stress in a semiconductor die resulting from stress within a top side protective layer.
2. State of the Art
An individual integrated circuit semiconductor die is usually formed from a larger structure known as a semiconductor wafer. Wafers are usually formed by slicing a large cylindrically shaped crystal of silicon, although other materials such as gallium arsenide and indium phosphide are also used. The front side or surface of the wafer is first ground and polished to a smooth surface, for fabrication of multiple integrated circuits thereon. Each semiconductor wafer has a plurality of integrated circuits arranged in rows and columns with the periphery of each integrated circuit typically being substantially rectangular. In the electronics industry, there is a need for apparatus of smaller size, higher performance and higher memory storage. These factors drive the industry to produce smaller semiconductor dice by thinning each wafer, i.e., reducing the cross section using a mechanical and/or chemical grinding process or etching. After thinning, the wafer is sawn or diced into rectangularly shaped “dice” along two mutually perpendicular sets of parallel lines or streets separating each row and column of dice in the wafer. Thus, the individual integrated circuit semiconductor die in the form of semiconductor dice are singulated from the wafer.
Fabrication of the integrated circuits is performed on the active surface of the undivided wafer, and consists of various processes including known steps of layering, patterning, doping, etching and heat treatment, for example. Various layers applied to the active surface of the wafer typically include insulators, semiconductors and metallic conductors. The final layering step generally comprises the application of a passivation material to cover the integrated circuit with a smooth electrically insulative protective layer. The purpose of the passivation layer is to protect the electronic components on the active surface, i.e., front side during subsequent wafer thinning, die testing, die singulation from the wafer, die packaging, and use. Exemplary passivation materials include silicon dioxide and silicon nitride (doped or undoped with boron or phosphorus, for example), as well as other materials including polymer-based compositions as known in the art. Further protection from damage during thinning of the wafer back side may be provided by temporarily attaching an adhesive-backed polymer (e.g. vinyl) sheet to the front side of the wafer. Such is disclosed in U.S. Pat. No. 5,840,614 of Sim et al. and U.S. Pat. No. 6,030,485 of Yamada, in which a UV sensitive tape is attached to the active surface of a wafer and made removable by radiation following back side lapping. In U.S. Pat. No. 5,962,097 of Yamamoto et al., a protective member is removably attached to an active surface of a wafer by a pressure sensitive adhesive.
Wafer thinning is performed in order to (a) reduce the package size, (b) reduce the consumption of saw blades in subsequent die singulation from the wafer, and (c) remove any electrical junctions which have formed on the wafer back side during fabrication. The processes typically used for wafer thinning include mechanical grinding and chemical-mechanical polishing (CMP). Alternatively, etching may be used but is not generally preferred. Each of these processes requires protection of the front side or active surface of the wafer containing the electronic components of the semiconductor die and/or wafer. The wafer grinding/polishing step typically results in a somewhat rough back side which is not conducive to other semiconductor die manufacturing processes, such as direct laser marking of a semiconductor die.
Although wafer thinning produces semiconductor dice of much reduced size, it also tends to result in a higher incidence of semiconductor die breakage. In addition, stresses induced by any grinding and polishing processes must be carefully controlled to prevent wafer and semiconductor die warping or bowing. Wafer warp interferes with precise semiconductor die separation (singulation), and semiconductor die warping results in die-attach problems in subsequent packaging. In addition, warping may cause breakage of wire bonds, etc.
Stresses produced in a semiconductor die by application of a layer thereto may be classified as either “intrinsic” or result from “thermal mismatch” between the material of the semiconductor die and the material of the applied layer. In the former case, the applied layer may be in tensile or compressive stress as applied or cured. For example, a polymeric layer may shrink during a curing step to produce intrinsic compressive stress in the active surface of a semiconductor die to which it is attached. Stress resulting from thermal mismatch is particularly evident where the layer deposition is not done at room temperature. Upon cooling to ambient temperature or to a working temperature, different coefficients of expansion (CTE) result in differential contraction or expansion between the semiconductor die substrate, the wafer, and the applied layer. Each of these stress components is important in the fabrication of semiconductor die, particularly where the ratio of semiconductor die thickness to semiconductor die length (or width) is very low.
Application of an effective passivation layer to the front side of a wafer typically results in stresses in the wafer and the semiconductor die singulated therefrom. Stresses introduced by the passivation layer may be sufficient to produce undesirable warping in the semiconductor dice, particularly where the wafer has been thinned to a high degree. A rigid unwarped substrate is particularly critical in forming known-good-die (KGD) with wire bonds.
In one sawing method of singulation, the wafer back side is attached to a flexible plastic film to hold the individual semiconductor die in place during cutting. The film is subsequently separated and removed from the singulated semiconductor die, and has no effect upon die warping. In one version, the film is stretched to release the semiconductor dice, which are then simply picked off the film. The semiconductor dice may then be processed to form differing types of semiconductor packages.
In one commonly used die-attach method, an adhesive material (e.g., epoxy) is used to join the back side of a die to a carrier. The adhesive material may be insulative or be electrically conductive and heat conductive.
Layer formation on a wafer back side has been done for another purpose. Such layers have been applied to provide a smooth surface for marking a semiconductor die or wafer with indicia identifying the manufacturer, serial number, lot number, and/or bar code, for example.
Conventional laser marking techniques utilize a very high intensity beam of light to alter the surface of a semiconductor die by melting, burning, or ablating the device surface directly, or by discoloration or decoloration of a laser reactive coating applied to a surface of the bare semiconductor die or packaged semiconductor die. The beam of light may be scanned over the surface of the bare or packaged semiconductor die in the requisite pattern, or can be directed through a mask which projects the desired inscriptions onto the desired surface of the bare or packaged semiconductor die. The surface or coating of the semiconductor die thus modified, the laser marking creates a reflectivity difference from the rest of the surface of the semiconductor die.
Numerous methods for laser marking are known in the art. One method of laser marking involves applications where a laser beam is directed to contact the surface of a semiconductor device directly, as shown in U.S. Pat. No. 5,357,077 to Tsuruta, U.S. Pat. No. 5,329,090 to Woelki et al., U.S. Pat. No. 4,945,204 to Nakamura et al., U.S. Pat. No. 4,638,144 to Latta, Jr., U.S. Pat. No. 4,585,931 to Duncan et al., and U.S. Pat. No. 4,375,025 to Carlson.
Another method of laser marking makes use of various surface coating, e.g., carbon black and zinc borate, of a different color than the underlying device material. Two examples of this type of marking are described in U.S. Pat. No. 5,985,377 to Corbett and U.S. Pat. No. 4,707,722 to Folk et al.
In U.S. Pat. No. 5,866,644 to Mercx et al., molding compounds are disclosed which form products which may be laser marked. The molding compound contains a pigment as well as glass fibers for reinforcing the molded object.
The above-indicated methods have been found to be inadequate for marking the back side of a wafer or semiconductor die, inasmuch as the thinning methods, including mechanical grinding, chemical mechanical polishing, and etching all leave the back side in a nonsmooth condition with a surface topography unsuited for laser marking (with or without a thin surface coating).
Moreover, none of the coatings, if applied to the back side of a wafer or semiconductor die, will balance wafer stress or semiconductor die stress to prevent or significantly reduce warp.